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| 1 ps8382b 03/20/02 product pin configuration logic block diagram 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1 234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901 2 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI6C2502 product description the PI6C2502 features a low-skew, low-jitter, phase-locked loop (pll) clock driver. by connecting the feedback fb_out output to the feedback fb_in input, the propagation delay from the clk_in input to any clock output will be nearly zero. product features high-performance phase-locked-loop clock distribution for networking, synchronous dram modules for server/workstation/ pc applications allows clock input to have spread spectrum modulation for emi reduction zero input-to-output delay low jitter: cycle-to-cycle jitter 100ps max. on-chip series damping resistor at clock output drivers for low noise and emi reduction operates at 3.3v v cc wide range of clock frequencies up to 80 mhz package: plastic 8-pin soic package (w) 8-pin w phase-locked loop clock driver application if a system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as pi6c2509q, and pi6c2510q, is likely to be impractical. the device-to-device skew introduced can significantly reduce the performance. pericom recommends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. as shown in figure 1, this combination produces a zero-delay buffer with all the signal characteristics of the original zero-delay buffer, but with as many outputs as the non-zero-delay buffer part. for example, when combined with an eighteen output non-zero delay buffer, a system designer can create a seventeen-output zero-delay buffer. figure 1. this combination provides zero-delay between the reference clocks signal and 17 outputs clk_in fb_in pll av cc fb_out clk_out 1 2 3 v cc 4 clk_out clk_in gnd fb_in 8 7 6 5 agnd fb_out av cc 17 zero delay buffer PI6C2502 reference clock signal clk_out feedback 18 output non-zero delay buffer v
PI6C2502 phase-locked loop clock driver 2 ps8382 b 03/20/02 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 emanni pr ebmunni pe py tn oitpircsed ni_kl c8i . tupnikcolcecnerefe rn i_kl c. tupnikcolcmurtcepsdaerpsswolla ni_b f5i . tupnikcabdee fn i_b f. llplanretniehtotlangiskcabdeefehtsedivorp tuo_b f2o tuptuokcabdee ft uo_b f. kcabdeeflanretxerofdetacidedsi eulavemasehtforotsisergnipmad-seiresdeddebmenasahtuo_bf stuptuokcolcehts a. tuo_klc tuo_kl c3o foseipocweks-woledivorpstuptuoeseht.stuptuokcol c. ni_klc .rotsisergnipmad-seiresdeddebmenasahtuptuohcae va cc 7r ewop va.ylppusrewopgolana cc rofllpehtssapybotdesuoslaebnac vanehw.sesopruptset cc dessapybsillp,dnuorgotdeppartssi dn an i_kl c. stuptuoecivedehtotyltceriddereffubsi dng a1 d nuorg .yrtiucricgolanaehtrofecnereferdnuorgehtsedivorpdnga.dnuorggolana v cc 4r ewo p. ylppusrewop dn g6 d nuor g. dnuorg pin functions lobmy sr etemara p. ni m. xa ms tinu v i egnaregatlovtupni 5.0 ?v cc 5.0 +v v o egnaregatlovtuptuo i cd_o tnerructuptuocd 00 1a m rewo pt tanoitapissidrewopmumixam a 55= o riallitsni c0 . 1w t gts erutarepmetegarot s5 6 ?0 51 o c dc specifications (absolute maximum ratings over operating free-air temperature range) retemara ps noitidnoctse tv cc .ni m. py t. xa ms tinu i cc v i v= cc i;dngro o 0= )1( v6. 30 1 m a c i v i v= cc dngro v3.3 4 fp c o v o v= cc dngr o6 note: stress beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. note: 1. continuous output current PI6C2502 phase-locked loop clock driver 3 ps8382 b 03/20/02 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 recommended operating conditions lobmy sr etemara p. ni m. xa ms tinu v cc egatlovylppu s0 . 36 .3 v v hi egatlovtupnilevelhgi h0 .2 v li egatlovtupnilevelwol 8.0 v i egatlovtupn i0v cc t a erutarepmetria-eerfgnitarep o00 7c o lobmy sr etemara pn oitidno c. ni m. xa ms tinu i ho tnerrucpu-llup v tuo v4.2= - 81 am v tuo v0.2= - 03 i lo tnerrucnwod-llup v tuo v8.0 =5 2 v tuo v55.0 =7 1 electrical characteristics (over recommended operating free-air temperature range pull up/down currents, v cc = 3.0v) ac specifications timing requirements (over recommended ranges of supply voltage and operating free-air temperature) lobmy sr etemara p. ni m. xa ms tinu f clk ycneuqerfkcol c5 20 8z hm d cyi elcycytudkcolctupn i0 40 6% purewopretfaemitnoitazilibat s1s m retemara p) tupni(mor f) tuptuo(ot v cc c07-0,v3.0v3.3 =s tinu .ni m. py t. xam rettijtuohtiwrorreesahp tn i_klc - zhm66dnazhm001t an i_bf - 051 ?0 51+ sp elcyc-ot-elcyc,retti jz hm66dnazhm001t at uo_kl c0 01 ?0 01+ zhm001taweks zhm66dna tuo_kl cr ot uo_bf tuo_klc tuo_bfro 002 elcycytud tuo_klc tuo_bfro 5 45 5% v0.2otv4.0,emit-esir,rt 0.1 sn v4.0otv0.2,emit-llaf,ft 1.1 switching characteristics (over recommended ranges of supply voltage and operating free-air temperature, c l =30pf) note: these switching parameters are guaranteed by design. ! "# $ ! ! " " %$&'(&)* $ + ! , ! - . / ( (. & 0 1 2 ( (1' " "// 3 4 !5 6 789&&(9 & &9 + 6 789&&(9 & &9 $ " .(89 0, #: + ! 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 ! 5 ! + ! + + 9:6 06 " 9. primary signal layer (? oz. cu.) ground plane (1 oz. cu.) 5 mils 47 mils 5 mils prepreg core z = 60 ohms z = 60 ohms total board thickness = 62.6 prepreg power plane (1 oz. cu.) secondary signal layer (? oz. cu.) !5 ( (.6 ( (.; " 9& 0.014" 0.018" clock 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 agnd 4.7? 1.5? .002? .22? 4.7? .002? .22? 3.3v power supply vcc clk_out clk_in input_clock 25-150 mhz avcc board avcc fb_in 5-12pf feedback capacitor decoupling capacitors series terminating resistor PI6C2502 1.5? fb_out gnd avcc island for pi6c2510 avcc gnd c r c c cfb clk_in agnd agnd agnd gnd vcc use wider traces for ground and power (0.034-inch width, 0.1-inch pitch) legend: gnd = via to digital ground agnd = via to analog ground vcc = via to 3.3v digital power avcc = via to 3.3v analog power r = termination resistor 12-32 ? c = decoupling capacitor l = inductor cfb = feedback capacitor l c c c PI6C2502 gnd agnd fb_out fb_in clk_out l 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 !""#$%%&&&'# ()'() .0040 .0098 seating plane .013 .020 .050 bsc .016 .0075 .0098 1 8 .0099 .0196 0-8? .050 .149 .157 x.xx x.xx denotes dimensions in millimeters 3.78 3.99 .189 .196 4.80 5.00 1.27 .016 .026 1.35 1.75 .2284 .2440 5.80 6.20 0.406 0.660 0.330 0.508 0.10 0.25 0.40 1.27 0.19 0.25 0.25 0.50 x 45? .053 .068 ref |
Price & Availability of PI6C2502
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